View K9F2808U0B-DCB0_1749942.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

flash memory 1 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 document title 16m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 0.1 0.2 0.3 remark advance k9f2808q0b : preliminary history initial issue. k9f2808u0b(3.3v device )?s qualification is finished k9f2808q0b (1.8v device ) - changed typical read operation current (icc1) from 8ma to 5ma - changed typical program operation current (icc2) from 8ma to 5ma - changed typical erase operation current (icc3) from 8ma to 5ma - changed typical program time(tprog) from 200us to 300us - changed ale to re delay (id read, tar1) from 100ns to 20ns - changed cle hold time(tclh) from 10ns to 15ns - changed ce hold time(tch) from 10ns to 15ns - changed ale hold time(talh) from 10ns to 15ns - changed data hold time(tdh) from 10ns to 15ns - changed ce access time(tcea) from 45ns to 60ns - changed read cycle time(trc) from 50ns to 70ns - changed write cycle time(twc) from 50ns to 70ns - changed re access time(trea) from 35ns to 40ns - changed re high hold time(treh) from 15ns to 20ns - changed we high hold time(twh) from 15ns to 20ns 1. device code is changed - tbga package information : ?b? --> ?d? ex) k9f2808q0b-bcb0 ,bib0 --> k9f2808q0b-dcb0,dib0 k9f2808u0b-bcb0 ,bib0 --> k9f2808q0b-dcb0,dib0 2. v ih ,v il of k9f2808q0b(1.8 device) is changed (before revision) (after revision) input high voltage v ih i/o pins vccq-0.4 vccq except i/o pins v cc -0.4 - vcc input low voltage, all inputs v il - 0 - 0.4 input high voltage v ih i/o pins vccq-0.4 vccq +0.3 except i/o pins v cc -0.4 - vcc +0.3 input low voltage, all inputs v il - -0.3 - 0.4 draft date may 28?th 2001 jun. 30th 2001 jul. 30 th 2001 aug. 23th 2001 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.intl.samsungsemi.com/memory/flash/datasheets.html
flash memory 2 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.4 0.5 0.6 remark preliminary history 1. i ol (r/ b ) of 1.8v device is changed. -min. value: 7ma -->3ma -typ. value: 8ma -->4ma 2. ac parameter is changed. trp(min.) : 30ns --> 25ns 1. parameters are changed in 1.8v part(k9f2808q0b) . - tch is changed from 15ns to 20ns - tclh is changed from 15ns to 20ns - talh is changed from 15ns to 20ns - tdh is changed from 15ns to 20ns 1. parameters are changed in 1.8v part(k9f2808q0b) . - trp is changed from 25ns to 35ns - twb is changed from 100ns to 150ns - trea is changed from 40ns to 45ns draft date nov 5th 2001 feb 15th 2002 may 3rd 2002 note : for more detailed features and specifications including faq, please refer to samsung?s flash web site. http://www.intl.samsungsemi.com/memory/flash/datasheets.html
flash memory 3 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 general description features voltage supply - k9f2808q0b : 1.7~1.9v - k9f2808u0b : 2.7 ~ 3.6 v organization - memory cell array : (16m + 512k)bit x 8bit - data register : (512 + 16)bit x8bit automatic program and erase - page program : (512 + 16)byte - block erase : (16k + 512)byte 528-byte page read operation - random access : 10 m s(max.) - serial page access - k9f2808q0b : 70ns - k9f2808u0b : 50ns fast write cycle time - program time - k9f2808q0b : 300 m s(typ.) - k9f2808u0b : 200 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 100k program/erase cycles - data retention : 10 years command register operation package - k9f2808u0b-ycb0/yib0 : 48 - pin tsop i (12 x 20 / 0.5 mm pitch) - k9f2808x0b- dcb 0/ dib 0 63- ball tbga ( 9 x 11 /0.8mm pitch , width 1.0 mm) - k9f2808u0b-vcb0/vib0 48 - pin wsop i (12x17x0.7mm) * k9f2808u0b-v(wsopi ) is the same device as k9f2808u0b-y(tsop1) except package type. the k9f2808x0b is a 16m(16,777,216)x8bit nand flash memory with a spare 512k(524,288)x8bit. the device is offered in 1.8v or 3.3v vcc. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation pro- grams the 528-byte page in typical 200 m s and an erase operation can be performed in typical 2ms on a 16k-byte block. data in a page can be read out at 70ns/50ns(k9f2808q0b:70ns, k9f2808u0b:50ns) cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. the on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. even write-intensive systems can t ake advantage of the k9f2808x0b ? s extended reliability of 100k program/erase cycles by providing ecc(error correcting code) with real time mapping-out algorithm. the k9f2808x0b is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. product list part number vcc range organization pkg type k9f2808q0b- d 1.7 ~ 1.9v x8 tbga k9f2808u0b-y 2.7 ~ 3.6v tsop1 k9f2808u0b-d tbga k9f2808u0b- v wsop1 16m x 8 bit bit nand flash memory
flash memory 4 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 pin configuration (tsop1) k9f2808u0b-ycb0/yib0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c n.c n.c n.c gnd r/ b re ce n.c n.c vcc vss n.c n.c cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o7 i/o6 i/o5 i/o4 n.c n.c n.c vcc vss n.c n.c n.c i/o3 i/o2 i/o1 i/o0 n.c n.c n.c n.c package dimensions 48-pin lead plastic thin small out-line package type(i) 48 - tsop1 - 1220f unit :mm/inch 0.787 0.008 20.00 0.20 #1 #24 0 . 2 0 + 0 . 0 7 - 0 . 0 3 0 . 0 0 8 + 0 . 0 0 3 - 0 . 0 0 1 0 . 5 0 0 . 0 1 9 7 #48 #25 0 . 4 8 8 1 2 . 4 0 m a x 1 2 . 0 0 0 . 4 7 2 0 . 1 0 0 . 0 0 4 m a x 0 . 2 5 0 . 0 1 0 ( ) 0.039 0.002 1.00 0.05 0.002 0.05 min 0.047 1.20 max 0.45~0.75 0.018~0.030 0.724 0.004 18.40 0.10 0~8 ?? 0 . 0 1 0 0 . 2 5 t y p 0 . 1 2 5 + 0 . 0 7 5 0 . 0 3 5 0 . 0 0 5 + 0 . 0 0 3 - 0 . 0 0 1 0.50 0.020 ( )
flash memory 5 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 63-ball tbga (measured in millimeters) k9f2808x0b- dcb 0/ dib 0 r/b /we /ce nc ale /wp /re cle nc nc nc nc vcc nc nc i/o0 i/o1 nc nc vccq i/o5 i/o7 vss i/o6 i/o4 i/o3 i/o2 vss nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu dnu pin configuration (tbga) package dimensions (top view) 9.00 0.10 #a1 side view top view 0 . 9 0 0 . 1 0 0.45 0.05 4 3 2 1 a b c d g bottom view 1 1 . 0 0 0 . 1 0 63- ? 0.45 0.05 0 . 8 0 x 7 = 5 . 6 0 1 1 . 0 0 0 . 1 0 0.80 x5= 4.00 0.80 0 . 3 2 0 . 0 5 0.08max b a 2 . 8 0 2.00 9.00 0.10 (datum b) (datum a) 0.20 m a b ? 0 . 8 0 0 . 8 0 x 1 1 = 8 . 8 0 0.80 x9= 7.20 6 5 9.00 0.10 e f h
flash memory 6 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 pin configuration (wsop1) k9f2808u0b-vcb0/vib0 package dimensions 48-pin lead plastic very very thin small out-line package type (i) 48 - wsop1 - 1217f unit :mm 15.40 0.10 #1 #24 0 . 2 0 + 0 . 0 7 - 0 . 0 3 0 . 1 6 + 0 . 0 7 - 0 . 0 3 0 . 5 0 t y p ( 0 . 5 0 0 . 0 6 ) #48 #25 1 2 . 0 0 0 . 1 0 0 . 1 0 + 0 . 0 7 5 - 0 . 0 3 5 0.58 0.04 0.70 max (0.1min) 17.00 0.20 0 ~ 8 0.45~0.75 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 n.c n.c dnu n.c n.c n.c r/ b re ce dnu n.c vcc vss n.c dnu cle ale we wp n.c n.c dnu n.c n.c n.c n.c dnu n.c i/o7 i/o6 i/o5 i/o4 n.c dnu n.c vcc vss n.c dnu n.c i/o3 i/o2 i/o1 i/o0 n.c dnu n.c n.c
flash memory 7 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 pin description note : connect all v cc and v ss pins of each device to common power supply outputs. pin name pin function i/o 0 ~ i/o 7 data inputs/outputs the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high-z when the chip is deselected or when the outputs are disabled. cle command latch enable the cle input controls the activating path for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. ale address latch enable the ale input controls the activating path for address to the internal address registers. addresses are latched on the rising edge of we with ale high. ce chip enable the ce input is the device selection control. when the device is in the busy state, ce high is ignored, and the device does not return to standby mode in program or erase opertion. regarding ce control during read operation, refer to ?page read? section of device operation. re read enable the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re which also increments the internal column address counter by one. we write enable the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. wp write protect the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. r/ b ready/busy output the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. vccq output buffer power v cc q is the power supply for output buffer. vccq is internally connected to vcc, thus should be biased to vcc. vcc power v cc is the power supply for device. vss ground n.c no connection lead is not internally connected. gnd gnd input for enabling spare area to do sequential read mode including spare area , connect this input pin to vss or set to static low state or to do sequential read mode excluding spare area , connect this input pin to vcc or set to static high state. dnu do not use leave it disconnected.
flash memory 8 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 512b byte 16 byte figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the starting address of the 2nd half of the register. * a 8 is set to "low" or "high" by the 00h or 01h command. * l must be set to "low". * the device ignores any additional input of address cycles than reguired. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 a 22 a 23 *l v cc x-buffers command i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 23 a 0 - a 7 command ce re we wp i/0 0 i/0 7 vcc/v cc q v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 32k pages (=1,024 blocks) 512 byte 8 bit 16 byte 1 block =32 pages = (16k + 512) byte i/o 0 ~ i/o 7 1 page = 528 byte 1 block = 528 bytes x 32 pages = (16k + 512) byte 1 device = 528byte x 32pages x 1024 blocks = 132 mbits column address row address (page address) page register 128m + 4m bit nand flash array (512 + 16)byte x 32768 y-gating page register & s/a cle ale
flash memory 9 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 product introduction the k9f2808x0b is a 132mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528 columns. spare 16 columns are located in 512 to 527 column address. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected like nand structure. each of the 16 cells resides in a different page. a block consists of the 32 pages f ormed by one nand structures, totaling 8448 nand structures of 16 cells. the array organization is shown in figure 2. program and rea d operations are executed on a page basis, while erase operation is executed on a block basis. the memory array consists of 1024 blocks, and a block is separately erasable by 16k-byte unit. it indicates that the bit by bit erase operation is prohibited o n the k9f2808x0b. the k9f2808x0b has addresses multiplexed with 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except page program command and block erase command which require two cycles: one cycle for setup and another for execution. the 16m byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing: column address, low row address and high row address, in that order. page read and page program need the same three address cycles following required command input. in block erase operation, however, only two row address cycles are used. device operations are selected by writing specific commands into command register. table 1 defines the specific commands of the k9f2808x0b. table 1. command sets note : 1. the 00h command defines starting address of the 1st half of registers. the 01h command defines starting address of the 2nd half of registers. after data access on 2nd half of register by the 01h command, start pointer is automatically moved to 1st half register(00h) on the next cycle. caution : any undefined command inputs are prohibited except for above command set of table 1. function 1st. cycle 2nd. cycle acceptable command during busy read 1 00h/01h (1) - read 2 50h - read id 90h - reset ffh - o page program 80h 10h block erase 60h d0h read status 70h - o
flash memory 10 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 absolute maximum ratings note : 1. minimum dc voltage is -0.6v on input/output pins and -0.2v on vcc and vccq pins. during transitions, this level may undershoo t to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v ccq +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit k9f2808q0b(1.8v) k9f2808u0b(3.3v) voltage on any pin relative to v ss v in/out -0.6 to + 2.45 -0.6 to + 4.6 v v cc -0.2 to + 2.45 -0.6 to + 4.6 v v cc q -0.2 to + 2.45 -0.6 to + 4.6 v temperature under bias k9f2808x0b-ycb0, dcb 0 t bias -10 to + 125 c k9f2808x0b-yib0, dib 0 -40 to + 125 storage temperature t stg -65 to + 150 c recommended operating conditions (voltage reference to gnd, k9f2808x0b-ycb0, dcb 0:t a =0 to 70 c, k9f2808x0b-yib0, dib 0:t a =-40 to 85 c) parameter symbol k9f2808q0b(1.8v) k9f2808u0b(3.3v) unit min typ. max min typ. max supply voltage v cc 1.7 1.8 1.9 2.7 3.3 3.6 v supply voltage v cc q 1.7 1.8 1.9 2.7 3.3 3.6 v supply voltage v ss 0 0 0 0 0 0 v dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions k9f2808q0b(1.8v) k9f2808u0b(3.3v) unit min typ max min typ max operat- ing current sequential read i cc 1 ce =v il, i out =0ma k9f2808q0b: trc=70ns k9f2808u0b: trc=50ns - 5 15 - 10 20 ma program i cc 2 - - 5 15 - 10 20 erase i cc 3 - - 5 15 - 10 20 stand-by current(ttl) i sb 1 ce =v ih , wp =0v/v cc - - 1 - - 1 stand-by current(cmos) i sb 2 ce =v cc -0.2, wp =0v/v cc - 10 50 - 10 50 m a input leakage current i li v in =0 to vcc(max) - - 10 - - 10 output leakage current i lo v out =0 to vcc(max) - - 10 - - 10 input high voltage v ih i/o pins vccq-0.4 vccq+0 .3 2.0 - v cc q+0.3 v except i/o pins v cc -0.4 - vcc +0.3 2.0 - v cc +0.3 input low voltage, all inputs v il - -0.3 - 0.4 -0.3 - 0.8 output high voltage level v oh k9f2808q0b :i oh =-100 m a k9f2808u0b :i oh =-400 m a v cc q-0.1 - - 2.4 - - output low voltage level v ol k9f2808q0b :i ol =100ua k9f2808u0b :i ol =2.1ma - - 0.1 - - 0.4 output low current(r/ b ) i ol (r/ b ) k9f2808q0b :v ol =0.1v k9f2808u0b :v ol =0.4v 3 4 - 8 10 - ma
flash memory 11 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 mode selection note : 1. x can be v il or v ih. 2. wp should be biased to cmos high or cmos low for standby. cle ale ce we re wp mode h l l h x read mode command input l h l h x address input(3clock) h l l h h write mode command input l h l h h address input(3clock) l l l h h data input l l l h x data output l l l h h x during read(busy) on k9f2808u0b_y or k9f2808u0b_v x x x x h x during read(busy) on the devices except k9f2808u0b_y and k9f2808u0b_v x x x x x h during program(busy) x x x x x h during erase(busy) x x (1) x x x l write protect x x h x x 0v/v cc (2) stand-by capacitance ( t a =25 c, v cc =1.8v /3.3v , f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf valid block note : 1. the k9f2808x0b may include invalid blocks when first shipped. additional invalid blocks may develop while being used. the number of valid block s is presented with both cases of invalid blocks considered. invalid blocks are defined as blocks that contain one or more bad bit s . do not erase or program factory-marked bad blocks. refer to the attached technical notes for a appropriate management of invalid blocks. 2. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correct ion. parameter symbol min typ. max unit valid block number n vb 1004 - 1024 blocks ac test condition (k9f2808x0b-ycb0, dcb 0 :ta=0 to 70 c, k9f2808x0b-yib0, dib 0:ta=-40 to 85 c k9f2808q0b : vcc=1.7v~1.9v , k9f2808u0b : vcc=2.7v~3.6v unless otherwise noted) parameter k9f2808q0b k9f2808u0b input pulse levels 0v to vccq 0.4v to 2.4v input rise and fall times 5ns 5ns input and output timing levels vccq/2 1.5v k9f2808q0b:output load (vccq:1.8v +/-10%) k9f2808u0b:output load (vccq:3.0v +/-10%) 1 ttl gate and cl=30pf 1 ttl gate and cl=50pf k9f2808u0b:output load (vccq:3.3v +/-10%) - 1 ttl gate and cl=100pf program/erase characteristics parameter symbol min typ max unit program time t prog - k9f2808q0b:3 00 k9f2808u0b:200 500 m s number of partial program cycles in the same page main array nop - - 2 cycles spare array - - 3 cycles block erase time t bers - 2 3 ms
flash memory 12 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 ac timing characteristics for command / address / data input note : 1. if tcs is set less than 10ns, twp must be minimum 35ns, otherwise, twp may be minimum 25ns. parameter symbol k9f2808q0b k9f2808u0b unit min max min max cle set-up time t cls 0 - 0 - ns cle hold time t clh 20 - 10 - ns ce setup time t cs 0 - 0 - ns ce hold time t ch 20 - 10 - ns we pulse width t wp 25 (1) - 25 - ns ale setup time t als 0 - 0 - ns ale hold time t alh 20 - 10 - ns data setup time t ds 20 - 20 - ns data hold time t dh 20 - 10 - ns write cycle time t wc 70 - 50 - ns we high hold time t wh 20 - 15 - ns ac characteristics for operation note : 1. if reset command(ffh) is written at ready state, the device goes into busy for maximum 5us. 2. to break the sequential read cycle, ce must be held high for longer time than tceh. 3. the time to ready depends on the value of the pull-up resistor tied r/ b pin. parameter symbol k9f2808q0b k9f2808u0b unit min max min max data transfer from cell to register t r - 10 - 10 m s ale to re delay( id read ) t ar1 20 - 20 - ns ale to re delay(read cycle) t ar2 50 - 50 - ns cle to re delay t clr 50 - 50 - ns ready to re low t rr 20 - 20 - ns re pulse width t rp 35 - 25 - ns we high to busy t wb - 150 - 100 ns read cycle time t rc 70 - 50 - ns ce access time t cea - 60 - 45 ns re access time t rea - 45 - 35 ns re high to output hi-z t rhz 15 30 15 30 ns ce high to output hi-z t chz - 20 - 20 ns re high hold time t reh 20 - 15 - ns output hi-z to re low t ir 0 - 0 - ns we high to re low t whr 60 - 60 - ns device resetting time (read/program/erase) t rst - 5/10/500 (1) - 5/10/500 (1) m s k9f2808u0b-y only last re high to busy (at sequential read) t rb - 100 - 100 ns ce high to ready(in case of inter- ception by ce at read) t cry - 50 +tr(r/ b ) (3) - 50 +tr(r/ b ) (3) ns ce high hold time(at the last serial read) (2) t ceh 100 - 100 - ns
flash memory 13 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 nand flash technical notes identifying invalid block(s) invalid block(s) invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by samsung. the i nfor- mation regarding invalid block(s) is so called as the invalid block information. devices ,regardless of having invalid block(s), have the same quality level because all valid blocks have same ac and dc characteristics. an invalid block(s) does not affect the perfor - mance of valid block(s) because it?s bit line and common source line is isolated by a select transistor. the system design must be able to mask out invalid block(s) via address mapping. the 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require error correction. all device locations are erased(ffh) except locations where the invalid block(s) information is written prior to shipping. the i nvalid block(s) status is defined by the 6th byte in the spare area. samsung makes sure that either 1st or 2nd page of every invalid bl ock has non-ffh data at the column address of 517. since invalid block information is also erasable in most cases, it is impossible to recover the information once it was erased. therefore, system must be able to recognize the invalid block(s) based on the origin al invalid block information and create invalid block table via the following suggested flow chart(figure 3). any intentional erasu re of the original invalid block information is prohibited. * check "ffh" at the column address 517 figure 3. flow chart to create invalid block table. start set block address = 0 check "ffh" ? increment block address last block ? end no yes yes create (or update) no invalid block(s) table of the 1st and 2nd page in the block
flash memory 14 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 nand flash technical notes (continued) program flow chart start i/o 6 = 1 ? write 00h i/o 0 = 0 ? no * if ecc is used, this verification write 80h write address write data write 10h read status register write address wait for tr time verify data no program completed or r/b = 1 ? program error yes no yes * program error yes : if program operation results in an error, map out the block including the page in error and copy the target data to another block. * operation is not needed. error in write or read operation within its life time, the additional invalid blocks may develop with nand flash memory. refer to the qualification report for actual data. the following possible failure modes should be considered to implement a highly reliable system. in the case of status rea d fail- ure after erase or program, block replacement should be done. because program status fail during a page program does not affect the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased empty block and reprogramming the current target data and copying the rest of the replaced block. to improve the efficiency of mem- ory space, we recommend using ecc without any block replacement in read or verification failure due to single bit error case. th e said additional block failure rate does not include those reclaimed blocks. failure mode detection and countermeasure sequence write erase failure status read after erase --> block replacement program failure status read after program --> block replacement read back ( verify after program) --> block replacement or ecc correction read single bit failure verify ecc -> ecc correction ecc : error correcting code --> hamming code etc. example) 1bit correction & 2bit detection
flash memory 15 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 erase flow chart start i/o 6 = 1 ? i/o 0 = 0 ? no * write 60h write block address write d0h read status register or r/b = 1 ? erase error yes no : if erase operation results in an error, map out the failing block and replace it with another block. * erase completed yes read flow chart start verify ecc no write 00h write address read data ecc generation reclaim the error page read completed yes nand flash technical notes (continued) block replacement * step1 when an error happens in the nth page of the block ?a? during erase or program operation. * step2 copy the nth page data of the block ?a? in the buffer memory to the nth page of another free block. (block ?b?) * step3 then, copy the data in the 1st ~ (n-1)th page to the same location of the block ?b?. * step4 do not further erase block ?a? by creating an ?invalid block? table or other appropriate scheme. buffer memory of the controller. 1st block a block b (n-1)th nth (page) 1 2 { ~ 1st (n-1)th nth (page) { ~ an error occurs.
flash memory 16 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 samsung nand flash has three address pointer commands as a substitute for the two most significant column addresses. ?00h? command sets the pointer to ?a? area(0~255byte), ?01h? command sets the pointer to ?b? area(256~511byte), and ?50h? command sets the pointer to ?c? area(512~527byte). with these commands, starting column address can be set to somewhere of a whole page(0~527byte). ?00h? or ?50h? is sustained until another address pointer command is entered. but, ?01h? command is effective only for one time operation. after any operation of read, program, erase, reset, power_up following ?01h? command, the address pointer returns to ?a? area by itself. to program data starting from ?a? or ?c? area, ?00h? or ?50h? command must be entered bef ore ?80h? command is written. a complete read operation prior to ?80h? command is not necessary. to program data starting from ?b? area, ?01h? command must be entered right before ?80h? command is written. 00h (1) command input sequence for programming ?a? area address / data input 80h 10h 00h 80h 10h address / data input the address pointer is set to ?a? area(0~255), and sustained 01h (2) command input sequence for programming ?b? area address / data input 80h 10h 01h 80h 10h address / data input ?b?, ?c? area can be programmed. it depends on how many data are inputted. ?01h? command must be rewritten before every program operation the address pointer is set to ?b? area(256~512), and will be reset to ?a? area after every program operation is executed. 50h (3) command input sequence for programming ?c? area address / data input 80h 10h 50h 80h 10h address / data input only ?c? area can be programmed. ?50h? command can be omitted. the address pointer is set to ?c? area(512~527), and sustained ?00h? command can be omitted. it depends on how many data are inputted. ?a?,?b?,?c? area can be programmed. pointer operation of k9f2808x0b table 2. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) "a" area 256 byte (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page register pointer select commnad (00h, 01h, 50h) pointer figure 4. block diagram of pointer operation
flash memory 17 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 system interface using ce don?t-care. ce we t wp t ch t cs start add.(3cycle) 80h data input ce cle ale we i/o 0 ~ 7 data input ce don?t-care ? ? 10h for an easier system interface, ce may be inactive during data-loading or sequential data-reading as shown below. the internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. in addition , for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating ce during the data-loading and read- ing would provide significant saving in power consumption. start add.(3cycle) 00h ce cle ale we i/o 0 ~ 7 data output(sequential) ce don?t-care ? r/ b t r re t cea out t rea ce re i/o 0 ~ 7 figure 5. program operation with ce don?t-care. figure 6. read operation with ce don?t-care. on k9f2808u0b_y or k9f2808u0b_v ce must be held low during tr
flash memory 18 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle t cls t cs t clh t ch t wp t als t alh t ds t dh ce we cle ale i/o 0 ~ 7 a 0 ~a 7 t cls t cs t wc t wp t als t ds t dh t alh t als t wh a 9 ~a 16 t wc t wp t ds t dh t alh t als t wh a 17 ~a 23 t wp t ds t dh t alh
flash memory 19 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t dh t ds t dh t ds t dh t wp t wh t wp t wp * s erial access cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 dout dout dout t rc t rea t rr t oh t rea t reh t rea t oh t rhz ? ? ? ? ? ? ? notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. t rhz t chz t rp
flash memory 20 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 * status read cycle ce we cle re i/o 0 ~ 7 70h status output t clr t clh t cs t wp t ch t ds t dh t rea t ir t oh t oh t whr t cea t cls note : 1) is only valid on k9f2808u0b_y or k9f2808u0b_v read1 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 24 dout n dout n+1 dout n+2 dout n+3 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz dout 527 t rb t cry t wc ? ? ? 1) 1) on k9f2808u0b_y or k9f2808u0b_v ce must be held low during tr t ceh t rhz t chz t oh t oh
flash memory 21 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 23 dout dout 527 m address 511+m dout 511+m+1 t ar2 t r t wb t rr a 0 ~a 3 : valid address a 4 ~a 7 : don t care ? ? selected row start address m 512 16 page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 23 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data serial input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? on k9f2808u0b_y or k9f2808u0b_v ce must be held low during tr
flash memory 22 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 block erase operation (erase one block) manufacture & device id read operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech device t rea address. 1cycle ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 23 a 9 ~ a 16 auto block erase erase command read status command i/o 0 =1 error in erase doh 70h i/o 0 busy t wb t bers i/o 0 =0 successful erase page(row) address t wc ? setup command t ar1 t clr device device code* k9f2808q0b 33h k9f2808u0b 73h code*
flash memory 23 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 device operation page read upon initial device power up, the device status is initially read1 command(00h) latched. this operation is also initiated by wr iting 00h to the command register along with three address cycles. once the command is latched, it does not need to be written for the fol- lowing page read operation. two types of operation are available : random read, serial page read. the random read mode is enable d when the page address is changed. the 528 bytes of data within the selected page are transferred to the data registers in less t han 10 m s(tr). the system controller can detect the completion of this data transfer(tr) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out by sequential re pulse of 70ns/50n(k9f2808q0b:70ns, k9f2808u0b:50ns) period cycle. high to low transitions of the re clock take out the data from the selected column address up to the last column address. read1 and read2 commands determine pointer which selects either main area or spare area. the spare area(512 to 527 bytes) may be selectively accessed by writing the read2 command. addresses a 0 to a 3 set the starting address of spare area while addresses a 4 to a 7 are ignored. to move the pointer back to the main area, read1 command(00h/01h) is needed. figures 7 through 8 show typical sequence and timing for each read operation. figure 7,8 details the sequence. sequential row read is available only on k9f2808u0b_y or k9f2808u0b_v : after the data of last column address is clocked out, the next page is automatically selected for sequential row read. waiting 1 0 m s again allows reading the selected page. the sequential row read operation is terminated by bringing ce high. unless the operation is aborted, the page address is automatically incremented for sequential row read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the sequential read 1 and 2 operation is allowed only within a block and after the last pa ge of a block is readout, the sequential read operation must be terminated by bringing ce high. when the page address moves onto the next block, read command and address must be given. figures 7-1, 8-1 show typical sequence and timings for sequential row read operation. figure 7. read1 operation start add.(3cycle) 00h a 0 ~ a 7 & a 9 ~ a 23 data output(sequential) (00h command) data field spare field ce cle ale r/ b we i/o 0 ~ 7 re t r * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. (01h command)* data field spare field 1st half array 2st half array 1st half array 2st half array on k9f2808u0b_y or k9f2808u0b_v ce must be held low during tr
flash memory 24 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 figure 8. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 23 data output(sequential) spare field ce cle ale r/ b we data field spare field start add.(3cycle) (a 4 ~ a 7 : don t care) i/o 0 ~ 7 re t r 1st half array 2nd half array figure 7-1. sequential row read1 operation ( only for k9f2808u0b-y and k9f2808u0b-v, valid within a block ) 00h 01h a 0 ~ a 7 & a 9 ~ a 24 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) t r t r t r ? (gnd input =l, 00h command) data field spare field (gnd input =l, 01h command) data field spare field (gnd input=h , 00h command) data field spare field 1st half array 2nd half array 1st 2nd nth 1st half array 2nd half array 1st 2nd nth block 1st half array 2nd half array 1st 2nd nth on k9f2808u0b_y or k9f2808u0b_v ce must be held low during tr
flash memory 25 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 page program the device is programmed basically on a page basis, but it allows multiple partial page program of one byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page program operation within the same page without intervening erase operation should not exceed 2 for main array and 3 for spare array. the addressing may be done in any random order in a block. page program cycle consists of a serial data loading(up to 528 bytes of data) into the page register, and prog ram of loaded data into the appropriate cell. serial data loading can start in 2nd half array by moving pointer. about the pointer oper ation, please refer to the attached technical notes. serial data loading is executed by entering the serial data input command(80h) and three cycle address input and then serial data loading. the bytes except those to be programmed need not to be loaded. the page program confirm command(10h) initiates the programming process. writing 10h alone without previously entering 80h will not initi ate program process. the internal write controller automatically executes the algorithms and timings necessary for program and verif ica- tion, thereby freeing the cpu for other tasks. once the program process starts, the read status register command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b out- put, or the status bit(i/o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is completed, the write status bit(i/o 0) may be checked(figure 9). the internal write ver ifi- cation detects only errors for "1"s that are not successfully programmed to "0"s. the command register remains in read status co m- mand mode until another valid command is written to the command register. figure 9 details the sequence. figure 9. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 23 i/o 0 ~ 7 r/ b address & data input i/o 0 pass 528 byte data 10h 70h fail t prog figure 8-1. sequential row read2 operation (gnd input=fixed low) 50h a 0 ~ a 3 & a 9 ~ a 24 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (16byte) (16byte) data field spare field 1st block (a 4 ~ a 7 : don t care) 1st t r t r t r ? nth (only for k9f2808u0b-y and k9f2808u0b-v, valid within a block)
flash memory 26 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 figure 10. block erase operation block erase the erase operation is done on a block(16k bytes) basis. block erase is executed by entering erase setup command(60h) and 2 cycle block addresses and erase confirm command(d0h). only address a14 to a23 is valid while a9 to a13 is ignored. this two- step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise condition. at the rising edge of we after erase confirm command input, internal write controller handles erase and erase-veri- fication. when the erase operation is completed, the write status bit(i/o 0) may be checked. figure 10 details the sequence. 60h block add. : a 9 ~ a 23 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail t bers read status the device contains a status register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. after writing 70h command to command register, a read cycle takes out the content of the status register to the i/o pins on the falling edge of ce or re . this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be tog- gled for updated status. refer to table 3 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random read cycle, a read command(00 h or 50h) should be given before sequential page read cycle. i/o # status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 "0" i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table3. read status register definition
flash memory 27 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (73h) respectively. the command register remains in read id mode until further commands are issued to it. figure 11 shows the operation sequence. figure 12. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase mode, the reset operation will abort these operations. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 4 for device status after reset operation. if the device is already in reset state, new reset command will not be accepted by the command register. the r/ b pin transitions to low for trst after the reset command is written. reset command is not necessary for normal operation. refer to figure 12 below. after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b table4. device status t rst figure 11. read id operation ce cle i/o 0 ~ 7 ale re we 90h 00h ech address. 1cycle maker code device code t cea t ar1 t rea device t whr t clr device device code* k9f2808q0b 33h k9f2808u0b 73h code*
flash memory 28 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. it returns to high when the internal controller has finished the operatio n. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. because pull-up resistor value is related to tr(r/ b ) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(fig 13). its value c an be determined by the following g uidance. v cc r/ b open drain output device gnd rp t r , t f [ s ] i b u s y [ a ] rp(ohm) fig 13 rp vs tr ,tf & rp vs ibusy ibusy tr ibusy busy ready vcc @ vcc = 3.3v, ta = 25 c , c l = 100pf voh tf tr 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 100 tf 200 300 400 3.6 3.6 3.6 3.6 2.4 1.2 0.8 0.6 vol rp(min, 1.8v part) = v cc (max.) - v ol (max.) i ol + s i l = 1.85v 3ma + s i l where i l is the sum of the input currents of all devices tied to the r/ b pin. rp value guidance rp(max) is determined by maximum permissible limit of tr rp(min, 3.3v part) = v cc (max.) - v ol (max.) i ol + s i l = 3.2v 8ma + s i l 1.8v device - v ol : 0.1v, v oh : v cc q-0.1v 3.3v device - v ol : 0.4v, v oh : 2.4v t r , t f [ s ] i b u s y [ a ] rp(ohm) ibusy tr @ vcc = 1.8v, ta = 25 c , c l = 30pf 1k 2k 3k 4k 100n 200n 300n 3m 2m 1m 30 tf 60 90 120 1.7 1.7 1.7 1.7 1.7 0.85 0.57 0.43 c l
flash memory 29 k9f2808u0b-ycb0,yib0 K9F2808U0B-DCB0,dib0 k9f2808q0b-dcb0,dib0 k9f2808u0b-vcb0,vib0 the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 1.1v/2v(k9f2808q0b:1.1v, k9f2808u0b:2v). wp pin provides hardware pro- tection and is recommended to be kept at v il during power-up and power-down and recovery time of minimum 1 m s is required before internal circuit gets ready for any command sequences as shown in figure 14. the two step command sequence for program/ erase provides additional software protection. figure 14. ac waveforms for power transition v cc wp high ? ? k9f2808q0b : ~ 1.5v we data protection & powerup sequence k9f2808u0b : ~ 2.5v k9f2808q0b : ~ 1.5v k9f2808u0b : ~ 2.5v 10 m s ? ?

▲Up To Search▲

Price & Availability of K9F2808U0B-DCB0

	To Download K9F2808U0B-DCB0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .